1. Field of the Invention
The present invention relates generally to a method for manufacturing a semiconductor device, and more particularly, to a method for fabricating a contact pad of a semiconductor device.
2. Description of the Related Art
In the manufacturing process of memory devices in integrated circuits (IC), such as dynamic random access memory (DRAM) devices and static random acess memory (SRAM) devices, an electrically conductive material layer, called a contact pad, may be formed for establishing an electrical connection between a bit line and a drain, and an electrical connection between a capacitor and a source. Advantageously, the contact pad increases an area contacted in the electric connection between the bit line and the drain, and the electric connection between the capacitor and the source.
FIGS. 1 through 4 are drawings illustrating a conventional method for forming a contact pad of a semiconductor device.
Referring to FIG. 1, a gate structure 20 is formed on a semiconductor substrate 10 on which a device 12 is formed. The gate structure 20 is formed of a gate electrode 26, a silicide layer 24, a gate upper dielectric layer 22, and a gate spacer 28. A stopping layer 14 is formed at a substantially constant thickness along the surface of the semiconductor substrate, and an interdielectric layer 16 is deposited over the entire surface of the semiconductor substrate. Then, the interdielectric layer 16 is planarized by a chemical mechanical polishing (CMP) process or a reflow process. Usefully, the CMP allows a thickness of the interlayer dielectric 16 equal to or more than 1000 xc3x85 (xe2x80x9cT1xe2x80x9d in FIG. 1) to remain on the gate upper dielectric layer 22 in order to prevent an upper portion of the gate upper dielectric layer 22 from being damaged.
Referring to FIG. 2, an anti-reflective layer 18 is disposed over the interdielectric layer 16, and a patterned photoresist 30 is formed on the anti-reflective layer 18 for etching the contact pad.
Referring to FIG. 3, a portion of interdielectric layer 16 is etched and removed by a self aligned contact (SAC) using the patterned photoresist 30 as an etching mask, forming a lower interdielectric layer 16A. This forms a region in which a contact pad will be formed. A remaining portion 14A of the stopping layer 14 is used as an etch-stop for the SAC etching; and some part of the remaining portion 14A of stopping layer is further removed. A conductive material 34, for example, polysilicon, is deposited on which the stopping layer 14A is removed, filling the region 32 in which a control pad will be formed. Dry etching is performed again for easy operation of the following CMP process, and the deposited conductive material 34 for the contact pad, and the lower interdielectric layer 16A are etched back to a prescribed thickness (xe2x80x9cT2xe2x80x9d of FIG. 3).
Referring to FIG. 4, the CMP process is performed, and contact pads 34xe2x80x2 separated by gate structures 20 are formed. Here, the stopping layer 14B and the gate upper dielectric layer 22 act as a polishing stopper during the CMP process of the polished lower interdielectric layer 16B.
However, the method for fabricating a contact pad of a semiconductor device according to the conventional art has certain drawbacks.
For example, the process is rather complex. Moreover, part of the gate upper dielectric layer 22 is consumed by polishing or etching during the CMP process for manufacturing the contact pad. This may result in shorting of the contact pad 34xe2x80x2 and the silicide 24. This ultimately will result in shorting of the gate and bit line of the semiconductor device.
Finally, in order to prevent the gate upper dielectric layer from becoming too thin, a relatively thick gate upper dielectric layer 22 may be formed. As such, the thickness of the interdielectric layer 16 must be increased. An increase in the thickness of the interdielectric layer may result in the undesirable formation of voids within the interdielectric layer.
What is needed, therefore, is a method of fabricating a contact pad which overcomes the drawbacks of conventional techniques such as described above.
According to an illustrative embodiment of the present invention, a method of fabricating a contact pad of a semiconductor device includes forming a gate structure including a gate upper dielectric layer on a semiconductor substrate; forming a stopping layer over the semiconductor substrate; forming an interdielectric layer over the stopping layer; planarizing the interdielectric layer to expose at least the gate upper dielectric layer using a material which exhibits a high-polishing selectivity with respect to the interdielectric layer; etching the interdielectric layer in a region in which a contact pad will be formed on the semiconductor substrate; depositing a conductive material on the semiconductor substrate; and planarizing using a material which exhibits a high-polishing selectivity of the gate upper dielectric layer with respect to the conductive material.
Advantageously, in the CMP process for planarizing the interdielectric layer and the conductive material for the contact pad according to an illustrative embodiment of the present invention, because a slurry is used which gives a high polishing selectivity of the interdielectric layer with respect to the conductive material for the contact pad to the gate upper dielectric layer, the process can be simplified, and the loss in thickness of the gate upper dielectric layer can be minimized. As such, electrical shorting of the gate and the bit line can be prevented, and the process margin can be improved. Also, since the thickness of the interdielectric layer can be reduced by reducing the thickness of the gate upper dielectric layer, the occurrence of voids can be suppressed.